The size of a memory system, connected to a host system, is limited by the characteristics of the memory controller. These memory controllers are designed very simple for reasons of cost-effectiveness and they usually have the following characteristics:                up to 100 connector pins because inexpensive standard housings are used,        up to 10 chip select signals for the selection of memory chips,        up to 16 Kbytes internal RAM memory.        
Building larger systems with more than 10 memory chips requires additional external components, such as decoders, bus transceivers and possibly also RAM memory.
From patent application publication DE 102 27 256.5, for example, a system is known, wherein the memory chips of a larger memory unit are connected to a controller via additional components.
In patent document U.S. Pat. No. 6,397,314, a system of memory chips on a controller is described, wherein the controller has a double-wide data bus in order to supply two memory chips with data in parallel. This necessitates a non-standard memory controller, which requires additional connector pins. Furthermore, this system cannot be applied to still larger systems, since it is limited to two simultaneously addressable memory chips.